Field of the Invention
Embodiments of the present invention relate generally to semiconductor chip packaging and, more specifically, to a system for low-impedance power delivery for a packaged die.
Description of the Related Art
Advances in the design and fabrication of semiconductor devices has dramatically increased device speed but has, at the same time, led to significant challenges in the field of semiconductor packaging. These challenges are particularly acute with respect to minimizing the parasitic resistance, inductance, and capacitance effects introduced by the various interconnect elements of a semiconductor package, such as the power and ground planes, signal traces, packaging substrate vias, and microbumps that are electrically coupled to a packaged semiconductor die. More particularly, in the power delivery network of a packaged semiconductor die, parasitic effects caused by loop inductance between power and ground paths to the semiconductor die can be performance-limiting factors. Such inductance degrades signal quality and reduces the input/output bandwidth of the die.
Accordingly, there is a need in the art for a system that provides reduced impedance power delivery for a packaged die.